1. Field of the Invention
The present invention relates to a contact structure between two conductive layers in a semiconductor device and a method of manufacturing the same, and, more particularly, to a contact structure making two conductive layers in contact through an insulating layer having an opening and a method of manufacturing the same.
2. Description of the Background Art
So far a dynamic random access memory (DRAM) capable of randomly inputting/outputting data is known as a semiconductor device.
FIG. 23 is a sectional structure view for describing contact structure for interconnection in a conventional DRAM. Referring to FIG. 23, a DRAM includes a silicon substrate 41, thick isolating oxide films 43 formed spaced a predetermined distance away from each other on silicon substrate 41, n-type impurity diffused regions 49 formed on silicon substrate 41 between thick oxide films 43 and each forming a source/drain of a MOS transistor, n-type impurity diffused regions 44 formed adjacent to thick isolating oxide films 43, p-type impurity diffused regions 42 formed beneath respective isolating oxide films 43, cell plates 46 each formed on n-type impurity diffused region 44 with a capacitor gate insulating film 45 interposed therebetween, and gate electrodes 48 each formed on silicon substrate 41 between adjacent two n-type impurity diffused regions 49 with a gate oxide film 47 interposed therebetween. The DRAM further includes insulating oxide films 50 formed to cover the whole surface and having a contact hole 50a on one of n-type impurity diffused regions 49 constituting a MOS transistor, a polycrystalline silicon film 51a formed to cover insulating oxide films 50 and electrically connected to n-type impurity diffused region 49 in contact hole 50a, a refractory metal silicide film 52 formed on polycrystalline silicon film 51a, an interlayer insulating film 53 formed to cover the whole surface, and aluminum interconnecting layers 54 formed spaced a predetermined distance away from each other on interlayer insulating film 53.
Polycrystalline silicon film 51a is doped with impurities in order to reduce the resistance. n-type impurity diffused regions 44, capacitor gate insulating film 45, and cell plate 46 constitute a capacitor for storing an electric charge corresponding to a data signal. Polycrystalline silicon film 51 and refractory metal silicide film 52 constitute a bit line.
FIGS. 24 to 28 are sectional views for describing a manufacturing process (a first step to a fifth step) of a conventional DRAM illustrated in FIG. 23. FIG. 29 is a plan view of the DRAM in the second step of the manufacturing process illustrated in FIG. 25. FIG. 30 is a plan view of the DRAM in the fifth step of the manufacturing process illustrated in FIG. 28. FIG. 25 illustrates a section taken along line X--X in FIG. 29, and FIG. 28 illustrates a section taken along line X--X in FIG. 30.
Now, referring to FIGS. 23 to 30, a manufacturing process of contact structure for interconnection in a conventional DRAM will be described.
First, as illustrated in FIG. 24, p-type impurity ions are selectively implanted into a p-type silicon substrate 41. Then, p-type impurity diffused region 42 for preventing inversion and a thick isolating oxide film 43 are formed by thermal oxidation. n-type impurity ions are implanted into silicon substrate 41 by an ion implantation process or the like. n-type impurity diffused regions 44 are formed by heat treatment. A thin capacitor gate insulating film 45 is formed by a thermal oxidation process or a chemical vapor deposition process (CVD process). A polycrystalline silicon layer including impurities of a predetermined conductivity type is deposited on capacitor gate insulating film 45 by a CVD process or the like. The polycrystalline silicon layer is selectively removed by a photolithography technique to form a cell plate 46. Thus, a capacitor including n-type impurity diffused regions 44, capacitor gate insulating film 45, and cell plate 46 is formed.
A gate oxide film 47 is formed on p-type silicon substrate 41 by a thermal oxidation process or the like. A single layer of polycrystalline silicon or a two-layer film of polycrystalline silicon and refractory metal silicide layers is deposited on gate oxide film 47 by a CVD process or the like. This film is selectively removed by a photolithography technique. This causes gate electrodes 48 formed spaced a predetermined distance away from each other. Phosphorus ions, which are n-type impurities, are ion-implanted into silicon substrate 41 using gate electrode 48 and cell plate 46 as a mask. n-type impurity diffused layers 49 to be source/drain regions of a MOS transistor are formed by carrying out heat treatment. At this time, one of n-type impurity diffused regions 49 is formed to be connected to n-type impurity diffused region 44 included in a capacitor.
Next, as illustrated in FIG. 25, an insulating oxide film 50 is deposited on the whole surface by a reduced pressure CVD process or the like. Insulating oxide film 50 is selectively removed by a photolithography technique. Contact holes 50a are formed by doing this. Specifically, contact holes 50a are formed by carrying out selective etching by isotropic wet etching and anisotropic reactive ion etching (RIE) using a predetermined resist pattern formed on insulating oxide film 50 as a mask. A planar arrangement of thus formed contact holes 50a is illustrated in FIG. 29.
Next, as illustrated in FIG. 26, a polycrystalline silicon film 51 not doped with impurities is formed on the surface of n-type impurity diffused region 49 in contact hole 50a and the surface of insulating oxide film 50 by a reduced pressure CVD process. Polycrystalline silicon film 51 is formed to have a thickness of 1000 to 1500.ANG..
Next, as illustrated in FIG. 27, arsenic (As), which is n-type impurities, is diffused in the direction indicated by arrow 55 by an ion implantation process to reduce the resistance of polycrystalline silicon film 51.
Next, as illustrated in FIG. 28, a refractory metal silicide film 52 is formed on polycrystalline silicon film 51a doped with impurities. A bit line is implemented with polycrystalline silicon film 51a and refractory metal silicide film 52. A thick interlayer insulating film 53 is formed to cover the whole surface. A planar arrangement of the bit lines in this state is illustrated in FIG. 30.
Finally, as illustrated in FIG. 23, an aluminum layer is formed on interlayer insulating film 53 by a sputtering process. The aluminum layer is patterned by a photolithography technique. Aluminum interconnecting layers 54 as auxiliary word lines are formed in a direction corresponding to gate electrodes 48 as word lines.
As described above, the conventional contact structure for interconnection of a DRAM had n-type impurity diffused region 49 and polycrystalline silicon film 51a constituting a bit line formed to be electrically connected through contact hole 50a.
However, a problem as described in the following arouse in the conventional contact structure for interconnection. FIGS. 31 to 35 are sectional structure views for describing a formation process (a first step to a fifth step) of the polycrystalline silicon film illustrated in FIG. 26. FIG. 36 is a typical view illustrating a sectional structure of a CVD apparatus for forming the polycrystalline silicon film illustrated in FIG. 34.
Referring to FIGS. 31 to 36, a conventional problem will be described.
First, details of a formation process of the polycrystalline silicon film illustrated in FIG. 26 will be described.
As illustrated in FIG. 31, a contact hole 50a is formed in an insulating oxide film 50 so that a surface part 49a of an n-type impurity diffused region 49 is exposed. The exposed surface part 49a of n-type impurity diffused region 49 reacts with water (H.sub.2 O) or oxygen (O.sub.2) in the air. This causes a natural oxide film 61 to be formed on the surface of n-type impurity diffused region 49 as illustrated in FIG. 32. The thickness of natural oxide film 61 is approximately 10.ANG..
In a case where a polycrystalline silicon film is deposited on the structure by a CVD process in a state illustrated in FIG. 32, a CVD apparatus as illustrated in FIG. 36 is used. Referring to FIG. 36, a CVD apparatus includes a CVD furnace 71 and heaters 72 arranged in the periphery of CVD furnace 71. In operation, a wafer 73 in a state illustrated in FIG. 32 is inserted into CVD furnace 71 by machinery carriage.
When wafer 73 is inserted into CVD furnace 71 in a conventional CVD apparatus having such structure, outside air is caught in CVD furnace 71 together with wafer 73. The outside air caught therein includes oxygen O.sub.2. At this time, the temperature in CVD furnace 71 is a high temperature of at least 400.degree. C. Accordingly, the oxygen O.sub.2 caught in CVD furnace 71 and the high temperature atmosphere causes oxidation of the surface of wafer 73 to further proceed. Specifically, the exposed surface of n-type impurity diffused region 49 is further oxidized through natural oxide film 61. As a result, a thick oxide film 62 as illustrated in FIG. 33 is formed on the surface of n-type impurity diffused region 49. The thickness of thick oxide film 62 is approximately 20 to 30.ANG.. A polycrystalline silicon film 51 is formed by a CVD apparatus as illustrated in FIG. 34 on the structure in a state illustrated in FIG. 33. Then, as illustrated in FIG. 35, polycrystalline silicon film 51 (see FIG. 34) is doped with impurities. A polycrystalline silicon film 51a doped with impurities is formed by this. Then, a refractory metal silicide film 52 is formed on polycrystalline silicon film 51a by a sputtering process.
However, there was a problem that it is not possible to obtain satisfactory ohmic contact between n-type impurity diffused region 49 and polycrystalline silicon film 51a in the structure as illustrated in FIG. 35 because there is thick oxide film 62 therebetween. Now, ohmic contact will be described. FIG. 37 is a graph of current/voltage characteristics for describing ohmic contact. Referring to FIG. 37, ohmic contact is contact which makes it possible to obtain a linear proportional relationship between current and voltage. Contact which does not make it possible to obtain such linear proportional relationship is referred to as non-ohmic contact. In a contact structure for interconnection as illustrated in FIG. 35, n-type impurity diffused region 49 and polycrystalline silicon film 51a are brought to an non-ohmic contact state as illustrated in FIG. 37 because of the existence of thick oxide film 62. Thus, it was difficult to obtain a satisfactory ohmic contact between n-type impurity diffused region 49 and polycrystalline silicon film 51a because of thick oxide film 62 which is formed on the surface of n-type impurity diffused region 49 on the occasion of carriage into a CVD apparatus.
So far techniques of removing a naturally oxide film in a vacuum and forming a polycrystalline silicon film in the vacuum by a CVD process have been proposed. These are disclosed, for example, in "Paper presented at the 36th Annual Technical Meeting of the Institute of Environmental Sciences" pp.1-6. FIGS. 38 to 41 are sectional structure views for describing a proposed conventional formation process (a first step to a fourth step) of a polycrystalline silicon film using a CVD process. Referring to FIGS. 38 to 41, the proposed formation process of a polycrystalline silicon film will be simply described. First, as illustrated in FIG. 38, the surface of an n-type impurity diffused region 83 on a main surface of a silicon substrate 81 is exposed by a contact hole 82a formed in an insulating oxide film 82. Then, a natural oxide film 84 is formed on the surface of n-type impurity diffused region 83 in the same manner as the conventional one. Natural oxide film 84 is removed by etching in a vacuum as illustrated in FIG. 39. Then, as illustrated in FIG. 40, a polycrystalline silicon film 85 is formed by a CVD process in the vacuum. Thus, according to the proposed technique, no oxide film is formed between n-type impurity diffused region 83 and polycrystalline silicon film 85 when polycrystalline silicon film 85 is formed by a CVD process. Then, polycrystalline silicon film 85 (See FIG. 40) is doped with impurities, and a silicide film 86 is formed by sputtering as illustrated in FIG. 41. Then, an interlayer insulating film 87 of a PSG or BPSG film or the like is formed on the whole surface.
On the occasion of formation of interlayer insulating film 87, a reflow process in which processing is carried out in oxygen, hydrogen, and a high temperature atmosphere is used for flattening the surface of interlayer insulating film 87. Therefore, oxygen is supplied to the surface of silicon substrate 81, and an oxide film 88 is formed on the interface between silicon substrate 81 and insulating oxide film 82. If oxidation of oxide film 88 further proceeds, an oxide film is also formed on the interface between n-type impurity diffused region 83 and polycrystalline silicon film 85a. As a result, there is a problem that it is difficult to obtain satisfactory ohmic contact between n-type impurity diffused region 83 and impurity doped polycrystalline silicon film 85a. In addition, there is also a problem that high temperature processing on the occasion of formation of interlayer insulating film 87 causes the impurities with which impurity doped polycrystalline silicon film 85a is doped to be diffused into n-type impurity diffused region 83. If impurities are thus diffused from impurity doped polycrystalline silicon film 85a into n-type impurity diffused region 83, there is a problem that the impurity concentration of n-type impurity diffused region 83 changes. The change in the impurities in n-type impurity diffused region 83 cause various problems in a case where elements are miniaturized in accordance with integration of a semiconductor device. Specifically, in a case where n-type impurity diffused region 83 is a source/drain region of a MOS transistor, for example, diffusion of impurities from impurity doped polycrystalline silicon film 85a causes the space between the adjacent other source/drain region and it to be narrow. As a result, a problem that punch through tends to occur is also considered.
Now, a case where a bit line in a DRAM is implemented with only a silicide film will be considered.
FIGS. 42 to 46 are sectional structure views for describing a conventional formation process (a first step to a fifth step) of a silicide film by sputtering. Referring to FIGS. 42 to 46, a process of forming a silicide film to be a bit line by a sputtering process will be simply described.
First, as illustrated in FIG. 42, an n-type impurity diffused region 93 is formed in a predetermined region on the surface of a silicon substrate 91. An insulating oxide film 92 is formed so that a contact hole 92a is provided on a surface part 93a of n-type impurity diffused region 93. In a state in which surface part 93a of n-type impurity diffused region 93 is thus exposed, surface part 93a reacts with water or oxygen in the air. This causes a natural oxide film 94 to be formed as illustrated in FIG. 43. As illustrated in FIG. 44, natural oxide film 94 is removed by sputter etching. Subsequently, a silicide film 95 is formed by sputtering. In the case where a sputtering process is used like this, no oxide film is formed on the interface between silicide film 95 and n-type impurity diffused region 93.
However, if an interlayer insulating film 96 such as a PSG film is formed on silicide film 95 as illustrated in FIG. 46, the same problem as that in the case described with reference to FIG. 41 arises. Specifically, high heat treatment in an oxygen and hydrogen atmosphere on the occasion of formation of interlayer insulating film 96 causes an oxide film 97 to be formed on the interface between silicide film 95 and n-type impurity diffused region 93. There was a problem that this makes it impossible to obtain satisfactory ohmic contact. In addition, there was also a problem that high heat treatment on the occasion of formation of interlayer insulating film 96 causes the impurities in n-type impurity diffused region 93 to be diffused into silicide film 95. If impurities in n-type impurity diffused region 93 are diffused into silicide film 95, the impurity concentration of n-type impurity diffused region 93 is reduced. Therefore, there was a problem that the resistance of the contact between silicide film 95 and n-type impurity diffused region 93 is increased.
As described above, so far it was difficult to obtain satisfactory ohmic contact in contact structure between two conductive layers in a semiconductor device, and it was difficult to effectively prevent change in concentration of an impurity diffused region.